Test Scheduling of SoC by using Dynamic Voltage Frequency Scaling (DVFS) Technique

High temperature gradients in System on Chip (SoC) lowered the performances, reliability and leakage power. In addition, during testing gain more compared to normal operation. Therefore, investigation of impact dynamic voltage frequency scaling (DVFS) thermal aware test scheduling performance will be main contribution this work. The algorithm which embeds effect with supply is tested ITC’02 benchmark. formulation ILP minimize group session SoC continued DVFS formulation. Compared conventional thermal-aware approach based purely a scaling, technique provides shorter overall times greatly improved flexibility satisfy strict constraints. proposed task allows time than 46%.